As the demand for miniaturization, low manufacture cost, high density and multi-functionality of electronic products, chip packages continue to advance towards the package technology that a plurality of dies are encapsulated in one encapsulant.
An example of a switching voltage regulator will now be described to show some features of the prior package technology, with reference to FIG. 1A to 1C. As will be described below, the switching voltage regulator has a multi-chip package structure.
FIG. 1A illustrates a schematic diagram of an example structure of a switching voltage regulator. The switching voltage regulator includes a control chip u1, a top power switch Q1 and a bottom power switch Q2, all of which are independent components. For example, the top power switch and the bottom power switch are both MOSFETs. The control chip has 5 I/O terminals I/O1-I/O5, 2 driving terminals C1 and C2. The control chip provides signals from the driving terminals C1 and C2 to gates G1 and G2 of the two power switches Q1 and Q2 to control their on-off state. A drain of the power switch Q1 is electrically coupled to an input power supply VIN, a source of the power switch Q1 is electrically coupled to a drain of the power switch Q2, and a source of the power switch Q2 is grounded. The drain of the power switch Q2 provides an output signal LX. A chip package may be formed by the prior package technology, which incorporates the switching voltage regulator as shown in FIG. 1A. Top views of the resultant multi-chip package structure before and after encapsulation are shown in FIGS. 1B and 1C, respectively. In the multi-chip package structure shown in FIGS. 1B and 1C, the control chip u1 and the power switches Q1 and Q2 are substantially coplanar with each other, and arranged on a carrier of a leadframe. Pads of each chip are electrically coupled to the corresponding leads of the leadframe by bonding wires, so that the chip may be further electrically coupled to an external printed circuit board.
An important concern in the chip package technology is a ratio of a chip footprint to a package area. The package technology is advantageous if the ratio has a value of approximately 1. However, the above chip package structure means that the chip package has an area at least larger than a sum of the three independent chips. Consequently, it has a large package area and results in a high manufacture cost.